Integrated circuit packages typically consist of a plastic or ceramic substrate on which the integrated circuit is attached. The signal and power connections are made from the integrated circuit to conductive leads which span the distance between the interior of the chip carrier to the outer periphery or exterior to allow power and communication connections to be made to the circuitry outside the chip carrier. The conductive leads are typically manufactured as a group in a pattern described in the industry as a lead frame. In the construction of integrated circuit packages, it is common that a ceramic or plastic substrate is first manufactured and the lead frame is then bonded to the top of the substrate and the integrated circuit is attached to the center of the substrate. Bonding wires are then attached from the bonding pads of the integrated circuit to the conductive leads of the lead frame to make the electrical connections. Once the electrical connections are made a cap or cover for the substrate is bonded to the substrate covering the integrated circuit die, and a portion of the lead frame to form a hermetic seal. The outer portions of the leads are left exposed for connection to electrical circuitry external to the integrated circuit package.
There is a demand in the industry for increasingly dense circuitry on integrated circuit die and hence, increased numbers of pins on integrated circuit packages. Commensurate with this increased packing density is a demand for increased speed and performance from the integrated circuits. Increased packing density and speed of integrated circuits is a requirement of integrated circuit packages used in modern super-computers such as the type manufactured by Cray Research, Inc., the assignee of the present invention. Unfortunately decreased spacing between the leads on the lead frame placed on the substrate increases the capacitive coupling between the leads. This capacitive coupling has an adverse effect on the quality of signals which are transmitted on the leads. Capacitive loading on the leads may adversely affect the risetime, falltime, cause reflections, impedance mismatches, termination problems and a decrease in the speed at which signals may propagate into and out of the integrated circuit die as is well known to those skilled in the art. There is therefore a need in the prior art for an integrated circuit package which has an increased pin-out count with closely spaced leads of a lead frame, while at the same time having a reduced interlead capacitance. There is also a need in the prior art to carefully control the amount of interlead capacitance so that it falls within a predictable range of values.